It is generally understood that as transistor device size continues to decrease, device speeds in processors have continued to increase. When coupled with shorter clocking speeds (a.k.a. higher frequency), this has allowed processors to run at faster and faster speeds.
With the assumption of higher device speeds, the traditional processor design approach has been focused on defining the logical architecture, or pipeline, and the physical partitioning of the processor, with little up-front consideration of the ability to meet frequency requirements. However, as current process technologies, e.g. 65 nm and 45 nm, are beginning to reach theoretical limits of both device and interconnect speed, frequency analysis, or timing analysis, it is now a requirement of the high-level design stage to verify a given pipeline design will function within the given cycle time constraints.
In order to perform this analysis, a designer should convert a logical block, or “cone,” into a quantifiable unit of time, or “delay”, that can be summed and measured against the target cycle time. The actual delay of a given cone is a function of the number of inputs, or “conesize”, the critical delay path, and the speed of the physical processor components, all of which are subject to random change based on state of the inputs and process variation. As a result, a simple conversion function does not exist.
Because this type of analysis was previously not required, few or no solutions have been invented. One attempt at such a solution has been mental estimation of the logic delay, based on designer knowledge of logic structure and estimated gate delays. The drawback of this solution is that results require large human investment of time and may not be systematically regenerated.
Mental estimation of the logic delay is therefore usually impractical given design cycle time constraints, and stale estimations typically result in inaccurate analysis. As such, there is a need for a system and/or method of logical delay analysis that can be used to validate a pipeline architecture against a given cycle time and technology in the design phase.